This invention relates to semiconductor packaging and, particularly, to interconnect pad layout for flip chip interconnect.
Flip chip packages include a semiconductor die mounted onto a package substrate with the active side of the die facing the substrate. Interconnection of the circuitry in the die with circuitry in the substrate is made by way of bumps which are attached to an array of interconnect pads on the die, and bonded to a corresponding (complementary) array of interconnect pads on the substrate.
The pads on the die for the signal, power and ground functions of the die are conventionally distributed throughout the array, and the corresponding pads on the substrate are connected to appropriate circuitry to the external second level interconnects. The second level interconnects have a greater pitch than the flip chip interconnects, and so the routing on the substrate conventionally “fans out”. The fan out routing between the pads on the die and the external pins of the package is formed on multiple metal layers within the package substrate.
Multiple layer substrates are expensive, and in conventional flip chip constructs the substrate alone typically accounts for more than half the package cost (about 60% in some typical instances).
In conventional flip chip constructs the escape routing pattern typically introduces additional electrical parasitics, because the routing includes short runs of unshielded wiring and vias between wiring layers in the signal transmission path. Electrical parasitics can significantly limit package performance.